DUF=0, MICS=00, MOE=0
SAI MCLK Control Register
| RESERVED | no description available |
| MICS | MCLK Input Clock Select 0 (00): MCLK Divider input clock 0 selected. 1 (01): MCLK Divider input clock 1 selected. 2 (10): MCLK Divider input clock 2 selected. 3 (11): MCLK Divider input clock 3 selected. |
| RESERVED | no description available |
| MOE | MCLK Output Enable 0 (0): SAI_MCLK pin is configured as an input that bypasses the MCLK Divider. 1 (1): SAI_MCLK pin is configured as an output from the MCLK Divider and the MCLK Divider is enabled. |
| DUF | Divider Update Flag 0 (0): MCLK Divider ratio is not being updated currently. 1 (1): MCLK Divider ratio is updating on-the-fly. Furthur updates to the MCLK Divider ratio are blocked while this flag remains set. |